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參數(shù)：
| Rating | Automotive |
| Control method | External Control |
| Architecture | Gate Driver |
| Control interface | 6xPWM, 3xPWM |
| Gate drive (A) | 2.5 |
| Vs (Min) (V) | 5 |
| Vs ABS (Max) (V) | 95 |
| Features | 90-V DC motor pin sustainability, Active Short Circuit (ASC) protection |
| Operating temperature range (C) | -40 to 150 |
裝封、引腳、尺寸：
HTQFP (PAP) 64 100 mm² 10 x 10
特征：
- AEC-Q100 qualified for automotive applications:
- Device ambient temperature grade 0: –40°C to +150°C
- Device HBM ESD classification level 2
- Device CDM ESD classification level C4B
- Functional Safety-Compliant targeted
- Developed for functional safety applications
- Documentation to aid ISO 26262 system design will be available upon production release
- Systematic capability up to ASIL D targeted
- Three N-Channel half-bridge gate driver
- 2-A/2.5-A max peak gate drive current
- Power architecture optimized for 48-V applications
- 12-V/48-V split supply architecture
- 95-V transient absolute maximum rating of DC link power supply (DHCP)
- 105-V Bootstrap voltage to support 90-V MOSFET operating voltage range
- Bootstrap with charge pump for 100% duty cycle
- Integrated 1x (DRV3256A-Q1) or 3x (DRV3256-Q1) current shunt amplifirers
- Integrated configurable Active Short Circuit (ASC) function
- Low-side (DRV3256A-Q1) or Low-side and High-side (DRV3256-Q1/DRV3256B-Q1) ASC support
- Device pin control available
- Fault handling capability
- Serial peripheral interface (SPI)
- Supports 3.3-V and 5-V logic inputs
- protection features
- Battery voltage monitors
- MOSFET VDS overcurrent monitors
- Rshunt overcurrent monitors
- MOSFET VGS gate fault monitors
- Analog built in self test
- Internal regulator and clock monitors
- Device thermal warning and shutdown
- Fault condition indicator pin
說明：
The DRV3256-Q1 family of devices are highly-integrated three phase gate drivers for 48-V automotive motor drive applications. These devices are specifically designed to support high-power motor drive applications by providing 2-A peak source and 2.5-A peak sink gate drive currents, and 90-V MOSFET transient over voltage support. A highly efficient bootstrap architecture is used to minimize power losses and self-heating of the gate drivers. A charge pump allows for the gate drivers to support 100% PWM duty cycle control.
A wide range of diagnostics, monitoring, and protection features supports a robust motor drive system design. A highly configurable Active Short Circuit (ASC) function which enables selected external MOSFETs is integrated to achive the fast response to system faults and to eliminate the needs of external components.
Three or single low-side current shunt amplifiers are optionally provided to support resistor based low-side current sensing.
